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    • 专利摘要:
    The invention relates to a normally open type high electron mobility field effect transistor (1) comprising: superposition of a first layer of semiconductor material (15) and a second layer of semiconductor material; conductor (16) to form an electron gas layer (17) at the interface of the interface between these first and second layers; a trench (5) separating the superposition into first and second domains (51, 52); an insulating element (34) disposed in said trench for electrically isolating said first and second domains; a P-type doped semiconductor element (33) in contact with the first or second layer of semiconductor material (16) of the first and second domains (51, 52), and extending continuously between first and second domains; a gate insulator (32) disposed on the semiconductor element (33); a gate electrode (31) disposed on the gate insulator (32).
    公开号:FR3050869A1
    申请号:FR1653905
    申请日:2016-04-29
    公开日:2017-11-03
    发明作者:Yannick Baines；Julien Buckley
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    The invention relates to heterojunction power transistors, and in particular to heterojunction power transistors of normally open type. BACKGROUND OF THE INVENTION The invention relates to heterojunction power transistors, and in particular to heterojunction power transistors of normally open type.
    Numerous electronic applications now require performance improvements, especially in on-board electronics for the automotive and land transport industries, in aeronautics, in medical systems or in home automation solutions, for example. Most of these applications require high power switches operating in frequency ranges frequently greater than megahertz.
    Historically, power switches have long relied on field effect transistors based on a semiconductor channel, most often silicon. For lower frequencies, junction transistors are preferred because they support higher current densities. However, because of the relatively limited breakdown voltage of each of these transistors, the power applications require the use of a large number of series transistors, or longer transistors, which results in a higher throughput resistance. high. The losses through these series transistors are considerable, both in steady state and in commutation.
    An alternative for power switches, especially at high frequencies, is the use of heterojunction field effect transistors, also referred to as heterostructure field effect transistors. Such transistors include in particular the high electron mobility transistors known as HEMTs.
    In particular, a high electron mobility transistor includes the superposition of two semiconductor layers having different forbidden bands which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional gas of electrons. For reasons of resistance to high voltage and temperature, these transistors are chosen so as to have a wide band of forbidden energy.
    For certain applications, including safety applications for isolating a circuit in the event of a malfunction of a control system, normally-open or normally-blocked type HEMT transistors are used, that is, their voltage switching threshold is positive, so that the transistor remains blocked in the absence of a control signal. There is a need for such transistors having a relatively high threshold voltage, typically at least 3V.
    Because of the inherently conductive nature of the electron gas layer formed between a source and a drain, it is technologically easier to provide a normally-passed heterojunction transistor. However, several manufacturing processes have been developed to form normally open or normally blocked heterojunction transistors.
    US8664696 discloses a normally open type HEMT transistor. The transistor comprises the following stack of layers: a Saphire substrate; a nitride buffer layer formed on the substrate; an unintentionally doped layer of GaN formed on the buffer layer; a P-type doped GaN layer formed on the unintentionally doped GaN layer; an N-type doped GaN layer formed on the P-doped GaN layer; an N-type doped AIGaN layer formed on the N-type doped GaN layer.
    An electron gas layer is formed near the interface between the AIGaN layer and the N-type doped GaN layer. A source and a drain are formed in contact with the AIGaN layer. A trench is formed through the AIGaN layer through the N-type doped GaN layer and extends to the P-type doped GaN layer. A gate insulator is interposed between the pore-type GaN layers. the trench and a gate electrode formed inside the trench.
    On either side of the trench, the conduction towards the source and towards the drain is carried out through the layer of electron gas. The electron gas layer is interrupted by the gate trench.
    When the bias voltage of the gate is lower than the threshold voltage of the transistor, no conduction channel connects the two parts of the electron gas layer on either side of the gate trench.
    When the bias voltage of the gate is greater than the threshold voltage of the transistor, an inverting channel is formed in the P-type GaN layer under the gate trench. The electrons from the drain can then pass through this inversion channel to reach the source through the N-type GaN layer.
    Such a transistor has a relatively high threshold voltage and the P-doped GaN layer limits the parasitic electron conduction at depth by acting as a rear barrier.
    However, such a transistor has disadvantages. Indeed, the P-doped GaN layer is generally formed by epitaxy. The doping profile of this P-doped GaN layer is difficult to control, in particular when the dopant is magnesium. Moreover, for an N-doped GaN layer of reduced thickness, the electron gas is affected by the proximity of the P-doped GaN layer, which leads to a high conduction resistance of the transistor. On the other hand, for a layer of N-doped GaN of high thickness, the trench must be deeper. Such trench depth induces transition resistances around the bottom of the trench, leading to a high conduction resistance of the transistor. In addition, a high conduction resistance is obtained through the epitaxially grown P-doped GaN layer prior to trench formation. The invention aims to solve one or more of these disadvantages. The invention thus relates to a normally open type high electron mobility field effect transistor, comprising: a superposition of a first layer of III-V alloy semiconductor material and a second layer of material a III-V alloy semiconductor so as to form a layer of electron gas at or near the interface between said first and second layers; a trench separating the superposition of the first and second layers of semiconductor material into first and second domains; an insulating element disposed in said trench so as to electrically isolate said first and second domains from the superposition; a P-type doped semiconductor element in contact with the second layer of semiconductor material of the first and second domains, and extending continuously between the first and second domains on said insulating element; a gate insulator disposed on the semiconductor element; a gate electrode disposed on the gate insulator. The invention also relates to the following variants. Those skilled in the art will understand that each of the features of the following variants may be independently combined with the above features, without necessarily constituting an intermediate generalization.
    According to one variant, the P-type doped semiconductor element is P-doped NiO.
    According to another variant, the P-type doped semiconductor element is made of P-doped polysilicon.
    According to another variant, the P-type doped semiconductor element is P-doped GaN.
    According to yet another variant, said P-type doped semiconductor element extends in said trench.
    According to a variant, said insulating element comprises a projection protruding vertically from the trench, and wherein said semiconductor element covers said projection.
    According to another variant, the transistor further comprises a third layer of P type doped semiconductor material, on which said first layer is formed, said trench extending into said third layer of semiconductor material, said trench having a depth of at least 100 nm and said first layer of semiconductor material having a thickness of at least 70 nm.
    According to another variant, the transistor further comprises a third layer of P type doped semiconductor material, on which said first layer is formed, said trench extending into said third layer of semiconductor material.
    According to another variant, the semiconductor element, the insulating element and the gate insulator are sufficiently thin so that the application of a threshold voltage on the gate electrode creates an inversion conduction channel in the gate. the third layer of semiconductor material under said trench.
    According to yet another variant, the first layer of semiconductor material is GaN.
    According to a variant, the second layer of semiconductor material is AIGaN.
    According to another variant, the transistor comprises a first conduction electrode electrically connected to the electron gas of the first domain, and comprising a second conduction electrode electrically connected to the electron gas of the second domain.
    According to another variant, said gate insulator has a thickness at most equal to 15 nm and / or in which said semiconductor element comprises a concentration of P-type dopant at least equal to 2 * 1017 cm-3. The invention also relates to a system, comprising: a field effect transistor as defined above; a control circuit configured to selectively apply a control voltage to said gate electrode, the magnitude of said control voltage generating a conductive inversion channel in said semiconductor element. The invention further relates to a method of manufacturing a heterojunction field effect transistor, comprising the steps of: providing a superposition of a first layer of III-V alloy semiconductor material and a second layer of III-V alloy semiconductor material forming an electron gas layer or a hole gas layer at or near the interface between these first and second layers, a trench separating superimposing the first and second layers of semiconductor material in first and second domains, an insulating member being disposed in said trench so as to electrically isolate said first and second domains from the superposition; forming a semiconductor element in contact with the first or second semiconductor material layer of the first and second domains and extending continuously between the first and second domains on the insulating element, the semiconductor element exhibiting P type doping; forming a gate insulator on the semiconductor element; forming a gate electrode on the gate insulator directly above the semiconductor element. Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the accompanying drawings, in which: FIG. 1 is a cross-sectional view of FIG. a normally open type HEMT transistor according to an example of a first embodiment of the invention, in open configuration; FIG. 2 is a cross-sectional view of the transistor of FIG. 1, in the closed configuration; FIG. 3 is a cross-sectional view of a normally open type HEMT transistor according to an example of a second embodiment of the invention, in open configuration; FIG. 4 is a cross-sectional view of the transistor of FIG. 3, in the closed configuration; FIG. 5 is a cross-sectional view of a normally open type HEMT transistor according to an example of a third embodiment of the invention, in open configuration; FIG. 6 is a cross-sectional view of the transistor of FIG. 5, in the closed configuration; FIG. 7 is a cross-sectional view of a normally open type high-mobility electronic transistor according to an example of a fourth embodiment of the invention, in open configuration; FIG 8 is a diagram illustrating various steps implemented during the manufacture of a transistor according to the invention.
    FIG. 1 is a cross-sectional view of a normally open type high mobility electronic transistor 1 according to an example of a first embodiment of the invention. In Figure 2, transistor 1 is shown in the on state. The broken line of Figure 2 illustrates the conduction path.
    The transistor 1 comprises a substrate 11. The substrate 11 may for example be an electrical insulator or an intrinsic silicon or p-doped semiconductor material. The substrate 11 may, for example, be of silicon type with a mesh orientation (111). The substrate 11 may also be silicon carbide, or sapphire. The substrate 11 may have a thickness of the order of 650 μm, typically between 500 μm and 2 mm.
    The transistor 1 here advantageously comprises one (or more) matching layer (not shown) disposed on the substrate 11. The matching layer may be deposited in a manner known per se on the substrate 11, and serves as an intermediate between the substrate 11 and a buffer layer of semiconductor material 12, to allow mesh matching between the substrate 11 and the layer 12. The matching layer may typically be aluminum nitride.
    The transistor 1 thus advantageously comprises a layer of semiconductor material 12 forming a so-called buffer layer whose function is the management of mechanical stresses and participating in the vertical electrical insulation of the structure. The layer 12 can be made via the use of a single semiconductor material III-N, such as unintentionally doped GaN. It can also be achieved by stacking different semiconductor materials III-N, such as a super AlxGai-xN / GaN network. The semiconductor layer 12 may typically have a thickness of between 100 nm and 5 μm. The semiconductor layer 12 may be formed in a known manner by either epitaxy on the matching layer.
    The transistor 1 comprises a layer 13 of semiconductor material of the III-V alloy type (for example a binary alloy of the III-V type, for example element III nitride, typically GaN) participating in the vertical electrical insulation. of the structure. The layer 13 may for example be of the type produced via the use of carbon-doped GaN. The layer 13 is here arranged on the buffer layer 12 and may typically have a thickness of 100 nm to 5 μm and a doping of 1 x 1018 cm 3 and 1 x 10 19 cm 3.
    The transistor 1 comprises a layer 14 made of a semiconductor material of the III-V alloy type (for example a P-type doped type III-V, for example type III nitride, typically GaN type). layer 14 forms a rear barrier or buried barrier (back barrier in English language). The layer 14 makes it possible to reduce the parasitic conduction of electrons in depth. The layer 14 is here disposed on the layer 13. The layer 14 may typically have a thickness of 50 nm to 200 nm and an Mg doping in the range of 1x1017 cm-3 and 1x1018cnrr3.
    The transistor 1 comprises a layer 15 of semiconductor material of the III-V alloy type (for example a binary alloy of the III-V type, for example element III nitride, typically GaN). The layer 15 is here formed on the layer 14. The layer 15 is for example GaN. The layer is for example a layer called GaN channel. The layer 15 is for example of the unintentionally doped or N + type doping type. The layer 15 may have a thickness typically between 50 and 500 nm.
    The transistor 1 may comprise a thin ALGai-xN layer between the so-called channel GaN layer 15 and the barrier layer 14. This layer may typically be AlN and may have a thickness close to 1 nm. This so-called spacer layer is intended to increase the confinement of the electron gas.
    The transistor 1 furthermore comprises a layer 16 made of semiconductor material of the III-V alloy type (for example a ternary alloy of the III-V type, for example of element III nitride, typically AIGaN or InAIN, or a quaternary alloy of element III nitride, for example AlxGayln (ixy) N, keeping a band gap greater than that of the material of the layer 15). The layer 16, typically called the barrier layer, can typically have a thickness of between 10 nm and 40 nm, for example 25 nm. The semiconductor layers 15 and 16 are superposed in a manner known per se to form a layer of electron gas 17 at the interface or near the interface between these layers 15 and 16.
    The transistor 1 further comprises a drain 21. The drain 21 is here formed on the layer 16. The drain 21 is electrically connected to the electron gas layer 17. In the example shown, the drain 21 is in contact with the layer 16. The transistor 1 further comprises a source 22. The source 22 is here formed on the layer 16. The source 22 is electrically connected to the electron gas layer 17. The drain 21 and the source 22 detailed are provided for illustrative purposes only and may have other types of structures and connections than those detailed in this example.
    The transistor 1 further comprises a control gate 3. The drain 21 and the source 22 are arranged on either side of the control gate 3. A trench 5 is formed under the control gate 3. The trench 5 crosses the layers 15 and 16 and thus interrupts the layer of electron gas 17. The trench 5 thus separates the superposition of the layers 15 and 16 and the layer of electron gas 17 in two disjoint domains 51 and 52. The trench 5 s here extends into the p-type doped layer 14.
    The transistor 1 comprises an insulating material element 34. The insulating material element 34 electrically isolates the domains 51 and 52 from the superposition of the layers 15 and 16. The element 34 interrupts in particular the electron gas layer 17 between the domains 51 and 52. The element 34 here covers the side walls of the trench 5 and is therefore in contact with the lateral faces of the layers 15 and 16. The element 34 here covers the bottom wall of the trench 5, and is therefore in contact with the layer 14 at the bottom of the trench 5. The element 34 also comprises flanges covering part of the layer 16 in the areas 51 and 52 respectively.
    The transistor 1 further comprises a p-type semiconductor element 33. The semiconductor element 33 is in contact with a layer of the stack of the layers 15 and 16 in the domain 51 on the one hand, and in the domain 52 on the other hand. In this example, the semiconductor element 33 is in contact with the layer 16 in the domain 51 on the one hand, and in the domain 52 on the other hand. The semiconductor element 33 thus comprises a portion 331 in contact with the layer 16 in the domain 51, and a portion 332 in contact with the layer 16 in the domain 52. Moreover, the semiconductor element 33 is extends continuously between the portions 331 and 332, that is to say between the domains 51 and 52. The semiconductor element 33 is here formed so as to cover the insulating element 34. The semiconductor element 33 is projecting laterally beyond the insulating element 34, to form the portions 331 and 332 in contact with the layer 16. The semiconductor element 33 has a portion housed in the trench 5, which covers the side walls and the bottom wall of the insulating member 34.
    The transistor 1 further comprises a gate insulator 32 formed on the semiconductor element 33. The transistor 1 furthermore comprises a gate electrode 31 arranged on the gate insulator 32. The gate electrode 31 is formed in FIG. the plumb with the semiconductor element 33. In particular, the projection of the gate electrode 31 on the substrate 11 in a direction normal to this substrate 11 includes the projection of the semiconductor element 33 on this substrate 11 in the normal direction to this substrate 11. Thus, the semiconductor element 33 is well positioned in the electromagnetic field of the gate electrode 31 when it is polarized. The control electrode 31 may be made in a manner known per se from metal (for example TiN) or doped polysilicon. The gate electrode 31 is electrically isolated from the drain 21 and the source 22 by an insulating layer 18, the insulating layer 18 being here formed on the layer 16 in the continuity of the gate insulator 32. control potential is selectively applied to the gate electrode 31 via a control circuit not shown. In FIG. 1, transistor 1 is illustrated in its configuration in the open or blocked state. The insulating element 34 and the semiconductor element 33 make the transistor 1 of the normally open type, the conduction between the domains 51 and 52 being interrupted when a potential applied to the gate electrode 31 is lower than the threshold voltage . The insulating element 34 effectively forms an electrical insulation between the domains 51 and 52 of the superposition of the layers 15 and 16. The semiconductor element 33 effectively provides electrical insulation between its portions 331 and 332 when the potential on the gate electrode 31 is less than the threshold voltage. Transistor 1 is therefore of normally open type.
    The distance between the portions 331 and 332 is typically less than 1 μm in order to limit the conduction path in the inversion layer. Moreover, it may be noted that the portions 331 and 332 of the semiconductor element 33 induce a local depletion in the layers 16 and 15 by the "pin" nature of the junctions formed by the stacking of the layers 33/16 / 15 at these places. A depletion 41 is thus formed under the portion 331, and a depletion 42 is thus formed under the portion 332. Under the trench 5, the P-type doped layer 14 forms a rear barrier to block a conduction between the domains 51 and 52 in the absence of bias on the gate electrode 31. The layer 14 thus contributes to the limitation of the lateral leakage current of the transistor 1 in the off state. It should be noted that the lateral leakage current will be greatly limited by: the absence of an electron channel in the p-type gate bias layer 33 below the threshold; the use of field plates in the grid-drain space of which the person skilled in the art is well aware. These field plates (not shown) are intended to accompany the lateral depletion of the two-dimensional electron gas in the grid-drain gap in the off state, as the drain voltage increases. The space charge zone thus created in the grid-drain space is a strong contributor to the limitation of lateral leakage currents. In Fig. 2, transistor 1 is illustrated in its closed or on state configuration. By applying a potential greater than the threshold voltage on the gate electrode 31, an inversion channel is formed in the semiconductor element 33. The semiconductor element 33 then allows the passage of the electrons from the zones 51 to 52. An electronic conduction path is thus created between the portion 331 and the portion 332 through the semiconductor element 33. The electron gas layers of the domains 51 to 52 are thus connected by a n-type conduction path. Conduction is thus provided between the drain 21 and the source 22 (as illustrated by the broken line).
    It may also be noted that the field applied to the gate electrode 31 suppresses the depletion zones 41 and 42 under the portions 331 and 332.
    In the embodiment illustrated, a potential on the gate electrode 31 greater than the threshold voltage may also make it possible to form a conductive link in the layer 14 under the trench 5. Such a conductive junction in the on state of the transistor 1 thus reduces its resistance in the on state. Such a conductive junction in the on state can for example be obtained with an insulating element 34, a semiconductor element 33 and a gate insulator 32 sufficiently fine.
    When the layers 15 and 16 are formed by epitaxy, the semiconductor element 33 can advantageously be formed outside the epitaxial framework, although a pGaN type epitaxy resumption is possible (expensive and complex). In particular, a semiconductor element 33 can easily be formed on the insulating element 34 outside an epitaxial frame, for example from a reactive sputtering deposit (for NiO for example) or a vapor phase deposition (for Polysilicon for example).
    The layer 15, intrinsic in its volume and n-type close to the interface with the layer 16 (place of the electron channel) forms with the layer 14, a NiP type junction. Thus, from domain 51 to domain 52, two Ni P junctions are connected to spit heads under the insulating element 34, a naturally blocking configuration in the absence of bias on the gate electrode 31.
    The trench 5 advantageously has a depth of at least 100 nm (measured between the upper face of the layer 16 and the bottom of the trench 5). The trench 5 advantageously has a width of at most 1 μm. The insulating element 34 is for example made of Al 2 O 3, SiO 2 or SiN. The insulating element 34 typically has a thickness between 10 nm and 200 nm.
    The choice of the p-type semiconductor element 33 is designed to meet the following selection criteria: 1. Large bandgap and doping capacity at high concentrations (1x1018 cnr3.): This favors obtaining a voltage high threshold (according to the MOSFET Theory) - 2. Conduction properties of the element 33, a low resistivity is sought: Thus the element 33 does not introduce a large series resistance, which avoids affecting the current to the passing state of the transistor. - 3. GaN channel / semiconductor potential barrier 33. The electronic affinity of the GaN and the semiconductor element 33 must be close (or have quasi-aligned conduction bands): this prevents the formation of a potential barrier at passage between the GaN and the element 33, which would reduce the current to the on state of the transistor. Satisfying these different criteria is difficult.
    P-NiO is favorable for criterion 1 or even 2.
    P-PolySi is favorable according to criteria 2 and 3. This material fulfills in part criterion 1 (low bandgap but high doping). The choice of p-PolySi will generally be favored.
    P-GaN is favorable according to criteria 1 and 3. The semiconductor element 33 is for example formed from a deposit of NiO, naturally doped material P. The NiO will for example be preferred for a transistor 1 to present a high threshold voltage due to its high forbidden band (3.4 eV) and the ability to strongly dope it (> 1x1018 cm-3). The semiconductor element 33 can also be formed from a deposit of P-doped polysilicon A polysilicon deposit will for example be preferred to promote increased electron mobility in the semiconductor element 33 in the on state. The polysilicon can in fact be doped with high concentrations in P type doping. The concentration of the P type doping in the polysilicon element 33 is advantageously between 2 * 1017cnrr3 and 1 * 1018cm-3, and advantageously between 3 * 1017cnrr3 and 8 * 1017cnrr3. The polysilicon furthermore has a better interface compatibility of the portions 331 and 332 with a layer 16 made of AIGaN. The forbidden band of polysilicon is typically of the order of 1.1 eV. Other P-type doped semiconductor materials may also be envisaged, for example P-type diamond. The semiconductor element 33 typically has a thickness of between 50 and 150 nanometers. The gate insulator 32 typically has a thickness of between 20 and 60 nanometers, for example 30 nm. The gate insulator 32 may be formed of a material such as SiO 2 or Al 2 O 3.
    In the first embodiment illustrated, it is also desired to be able to make a conductive junction under the trench 5 in the on state of the transistor 1. For this purpose, a thin insulating element 34 having a thickness of 30 nm for example, is advantageously used. and a relatively thin semiconductor element 33, typically less than 100 nm thick, for example. The gate insulator 32 will also preferably have a thickness of about 30 nm. The trench 5 will advantageously have a depth of less than 100 nm, preferably less than 80 nm.
    FIG. 3 is a cross-sectional view of a normally open type high mobility electronic transistor 1 according to an example of a second embodiment of the invention. In Figure 4, transistor 1 is shown in the on state. The broken line of Figure 4 illustrates the conduction path.
    In the second embodiment, it is desired to be able to block the formation of a conducting junction under a trench 5, even in the on state of the transistor 1. In this second embodiment, the transistor 1 comprises the following elements, identical to those of the first embodiment: the substrate 11; the adaptation layer; the layer of semiconductor material 12; the layer of semiconductor material 13.
    The transistor 1 advantageously comprises a layer 14 of semiconductor material of alloy type III-V (for example identical to that of the first embodiment) with P type doping. The layer 14 forms a rear barrier or buried barrier. The layer 14 makes it possible to reduce the parasitic conduction of electrons in depth. The layer 14 is here disposed on the layer 13.
    The transistor 1 comprises a layer 15 of semiconductor material of the III-V alloy type (for example identical to that of the first embodiment), formed on the layer 14. The layer 15 may have a thickness as described for the first embodiment, or a greater thickness.
    The transistor 1 further comprises a layer 16 of semiconductor material of the III-V alloy type (for example identical to that of the first embodiment). The layer 16 may have a thickness as described for the first embodiment. The semiconductor layers 15 and 16 are superposed in a manner known per se to form a layer of electron gas 17 at the interface or near the interface between these layers 15 and 16.
    The transistor 1 further comprises a drain 21 formed in contact on the layer 16 and electrically connected to the electron gas layer 17. The transistor 1 further comprises a source 22 formed in contact on the layer 16 and electrically connected to the layer of electron gas 17.
    The transistor 1 further comprises a control gate 3, the drain 21 and the source 22 being disposed on either side of the control gate 3. A trench 5 is formed under the control gate 3 and passes through the layers 15 and 16, thus interrupting the layer of electron gas 17. The trench 5 thus separates the superposition of the layers 15 and 16 and the layer of electron gas 17 into two disjoint domains 51 and 52. The trench 5 extends here in the p-type doping layer 14. The trench 5 can even extend beyond the layer 14.
    The transistor 1 comprises an insulating material element 34, electrically isolating the domains 51 and 52 from the superposition of the layers 15 and 16. The element 34 interrupts in particular the layer of electron gas 17 between the domains 51 and 52, covers the sidewalls of the trench 5 and is in contact with the lateral faces of the layers 15 and 16. The element 34 here covers the bottom wall of the trench 5, and is therefore in contact with the layer 14 at the bottom of the trench 5. The element 34 also includes flanges covering part of the layer 16 in the areas 51 and 52 respectively.
    The transistor 1 further comprises a P type doped semiconductor element 33 in contact with the layer 16 in the domain 51 on the one hand, and in the domain 52 on the other hand. The semiconductor element 33 thus comprises a portion 331 in contact with the layer 16 in the domain 51, and a portion 332 in contact with the layer 16 in the domain 52. Moreover, the semiconductor element 33 is extends continuously between the portions 331 and 332, that is to say between the domains 51 and 52. The semiconductor element 33 is here formed so as to cover the insulating element 34. The semiconductor element 33 is projecting laterally beyond the insulating element 34, to form the portions 331 and 332 in contact with the layer 16. The semiconductor element 33 has a portion housed in the trench 5, which covers the side walls and the bottom wall of the insulating member 34.
    The transistor 1 further comprises a gate insulator 32 formed on the semiconductor element 33. The transistor 1 furthermore comprises a gate electrode 31 arranged on the gate insulator 32. The gate electrode 31 is formed in FIG. the plumb with the semiconductor element 33. In particular, the projection of the gate electrode 31 on the substrate 11 in a direction normal to this substrate 11 includes the projection of the semiconductor element 33 on this substrate 11 in the normal direction to this substrate 11. Thus, the semiconductor element 33 is well positioned in the electromagnetic field of the gate electrode 31 when it is polarized. The control electrode 31 may be made of the same material as for the first embodiment. The gate electrode 31 is electrically isolated from the drain 21 and the source 22 by an insulating layer 18, formed on the layer 16 in the continuity of the gate insulator 32. A control potential is applied selectively to the gate electrode 31 via an unillustrated control circuit. In FIG. 3, transistor 1 is illustrated in its configuration in the open or blocked state. The insulating element 34 and the semiconductor element 33 make the transistor 1 of the normally open type, the conduction between the domains 51 and 52 being interrupted when a potential applied to the gate electrode 31 is lower than the threshold voltage . Furthermore, it can be noted that the portions 331 and 332 of the semiconductor element 33 can induce a field in the layer 16, leading to local depletion and additional electrical insulation, here at the interface between the portions 331,332 and the layer 16. A depletion 41 is thus formed under the portion 331, and a depletion 42 is thus formed under the portion 332. In Figure 4, the transistor 1 is illustrated in its configuration in the closed state or passing . By applying a potential greater than the threshold voltage on the gate electrode 31, an inversion channel is formed in the semiconductor element 33. The semiconductor element 33 then becomes conductive. A conduction path is thus created between the portion 331 and the portion 332 through the semiconductor element 33. An electrical connection is thus created between the electron gas layer 17 of the domains 51 and 52. Conduction is thus provided between the drain 21 and the source 22 (as illustrated by the broken line).
    With respect to the first embodiment, the transistor 1 comprises here: a trench 5 deeper, for example for a thicker layer 15. Such a thicker layer makes it possible to increase the distance between the electron gas layer 17 and the bottom of the trench 5, so that the resistance is increased if a conduction is to be formed under the trench 5. It is also possible to consider a layer 15 of the same thickness and a thicker layer 14; the thickness of the insulating element 34 and / or the semiconductor element 33 is increased, so that in the layer 14 under the trench 5, the electromagnetic field applied by the gate electrode 31 polarized at the Threshold voltage is not sufficient to form an inverting channel. The application of a threshold voltage on the gate electrode 31 does not then make it possible to obtain a conduction under the trench 5 via the layer 14.
    Trench 5 may have a depth greater than 200 nm and extend beyond layers 14 and 15 in depth. The thickness of the element 34 is 100 nm for example.
    FIG. 5 is a cross-sectional view of a normally open type high mobility electronic transistor 1 according to an example of a third embodiment of the invention. In Figure 6, transistor 1 is shown in the on state.
    In the third embodiment, it is desired to be able to block the formation of a conductive junction under a trench 5, even in the on state of the transistor 1. In this third embodiment, the transistor 1 comprises the following elements, identical to those of the first embodiment: the substrate 11; the adaptation layer; the layer of semiconductor material 12.
    The transistor 1 advantageously comprises a layer 13 of a III-V alloy type semiconductor material (for example a III-V type binary alloy, for example element III nitride, typically GaN). The layer 13 may for example be of the unintentionally doped or N type doping type. The layer 13 is here disposed on the buffer layer 12.
    The transistor 1 advantageously comprises a layer 14 of semiconductor material of alloy type III-V (for example identical to that of the first embodiment) with P type doping. The layer 14 forms a rear barrier or buried barrier. The layer 14 makes it possible to reduce the parasitic conduction of electrons in depth. The layer 14 is here disposed on the layer 13.
    The transistor 1 comprises a layer 15 of semiconductor material of the III-V alloy type (for example identical to that of the first embodiment), formed on the layer 14. The layer 15 advantageously has a thickness of at least 50 nm.
    The transistor 1 further comprises a layer 16 of semiconductor material of the III-V alloy type (for example identical to that of the first embodiment). The layer 16 may have a thickness as described for the first embodiment. The semiconductor layers 15 and 16 are superposed in a manner known per se to form a layer of electron gas 17 at the interface or near the interface between these layers 15 and 16.
    The transistor 1 further comprises a drain 21 formed in contact on the layer 16 and electrically connected to the electron gas layer 17. The transistor 1 further comprises a source 22 formed in contact on the layer 16 and electrically connected to the layer of electron gas 17.
    The transistor 1 further comprises a control gate 3, the drain 21 and the source 22 being disposed on either side of the control gate 3. A trench 5 is formed under the control gate 3 and passes through the layers 15 and 16, thus interrupting the layer of electron gas 17. The trench 5 thus separates the superposition of the layers 15 and 16 and the layer of electron gas 17 into two disjoint domains 51 and 52. The trench 5 also passes through the P-type doped layer 14. Trench 5 extends here into layer 13. Trench 5 advantageously has a depth of at least 200 nm.
    The transistor 1 comprises an insulating material element 34, electrically insulating the domains 51 and 52 of the superposition of the layers 15 and 16. The element 34 interrupts in particular the electron gas layer 17 between the domains 51 and 52. The element 34 fills the trench 5 to cover its side walls (and is in contact with the side faces of the layers 15 and 16) and cover its bottom wall. The element 34 is in contact with the layer 13. The element 34 has a protrusion 341 protruding vertically from the trench 5. The projection 341 thus protrudes vertically from the upper face of the layer 16. The element 34 also comprises flanges covering part of the layer 16 in the areas 51 and 52 respectively. The insulating element 34 may be formed of insulating material such as SiO 2 or Al 2 O 3. The insulating element 34 may also be formed of Argon-implanted semiconductor material directly in the III-N layers, allowing isolation, without the need for etching, semiconductor deposition and subsequent implantation.
    The transistor 1 further comprises a P type doped semiconductor element 33 in contact with the layer 16 in the domain 51 on the one hand, and in the domain 52 on the other hand. The semiconductor element 33 thus comprises a portion 331 in contact with the layer 16 in the domain 51, and a portion 332 in contact with the layer 16 in the domain 52. Moreover, the semiconductor element 33 is extends continuously between the portions 331 and 332, that is to say between the domains 51 and 52. The semiconductor element 33 is here formed so as to cover the insulating element 34 and in particular the projection 341. The semiconductor element 33 is integrally positioned above the layer 16 and has no part housed in the trench 5. The semiconductor element 33 projects laterally beyond the insulating element 34, for forming the portions 331 and 332 in contact with the layer 16.
    The transistor 1 further comprises a gate insulator 32 formed on the semiconductor element 33. The transistor 1 furthermore comprises a gate electrode 31 arranged on the gate insulator 32. The gate electrode 31 is formed in FIG. the plumb with the semiconductor element 33. In particular, the projection of the gate electrode 31 on the substrate 11 in a direction normal to this substrate 11 includes the projection of the semiconductor element 33 on this substrate 11 in the normal direction to this substrate 11. Thus, the semiconductor element 33 is well positioned in the electromagnetic field generated by the gate electrode 31 when it is polarized. The control electrode 31 may be made of the same material as for the first embodiment. The gate electrode 31 is electrically isolated from the drain 21 and the source 22 by an insulating layer 18, formed on the layer 16 in the continuity of the gate insulator 32. A control potential is applied selectively to the gate electrode 31 via an unillustrated control circuit. In FIG. 5, transistor 1 is illustrated in its configuration in the open or blocked state. The insulating element 34 and the semiconductor element 33 make the transistor 1 of the normally open type, the conduction between the domains 51 and 52 being interrupted when a potential applied to the gate electrode 31 is lower than the threshold voltage . Furthermore, it can be noted that the portions 331 and 332 of the semiconductor element 33 can induce a field in the layer 16, leading to local depletion and additional electrical insulation, here at the interface between the portions 331, 332 and the layer 16. A depletion 41 is thus formed under the portion 331, and a depletion 42 is thus formed under the portion 332. Moreover, because of the depth of the trench 5, parasitic conduction in the layer 13 under this trench 5 is greatly reduced. In FIG. 6, transistor 1 is illustrated in its configuration in the closed or on state. By applying a potential greater than the threshold voltage on the gate electrode 31, an inversion channel is formed in the semiconductor element 33. The semiconductor element 33 then becomes conductive. A conduction path is thus created between the portion 331 and the portion 332 through the semiconductor element 33, above the projection 341. An electrical connection is thus created between the electron gas layer 17 of the domains. 51 and 52. A conduction is thus provided between the drain 21 and the source 22. On the contrary, the conduction in the layer 13 under the trench 5 is prevented, in particular because of the depth of the trench 5, and because of the distance between the semiconductor element 33 and the bottom of the trench 5, the electromagnetic field applied by the gate electrode 31 on the layer 13 under the trench 5 being extremely reduced.
    FIG. 7 is a cross sectional view of a normally open type high mobility electronic transistor 1 according to an example of a second embodiment of the invention.
    In this fourth embodiment, the transistor 1 comprises the following elements, identical to those of the first embodiment: the substrate 11; the adaptation layer; the layer of semiconductor material 12; the layer of semiconductor material 13; the layer of semiconductor material 14; the layer of semiconductor material 15.
    The transistor 1 further comprises a layer 16 of semiconductor material of the III-V alloy type (for example identical to that of the first embodiment). The layer 16 may have a thickness as described for the first embodiment. The semiconductor layers 15 and 16 are superposed in a manner known per se to form a layer of electron gas 17 at the interface or near the interface between these layers 15 and 16.
    The transistor 1 further comprises a drain 21 formed in contact on the layer 16 and electrically connected to the electron gas layer 17. The transistor 1 further comprises a source 22 formed in contact on the layer 16 and electrically connected to the layer of electron gas 17.
    The transistor 1 further comprises a control gate 3, the drain 21 and the source 22 being disposed on either side of the control gate 3. A trench 5 is formed under the control gate 3 and passes through the layers 15 and 16, thus interrupting the layer of electron gas 17. The trench 5 thus separates the superposition of the layers 15 and 16 and the layer of electron gas 17 into two disjoint domains 51 and 52. The trench 5 extends here in the p-type doping layer 14. The trench 5 can even extend beyond the layer 14.
    The transistor 1 comprises a member of insulating material 34, electrically isolating the areas 51 and 52 of the superposition of the layers 15 and 16. The element 34 covers the side walls of the trench 5 and is therefore in contact with the lateral faces of the layer 15. The element 34 here covers the bottom wall of the trench 5, and is therefore in contact with the layer 14 at the bottom of the trench 5. The element 34 also comprises flanges covering a portion of the layer 15 in domains 51 and 52 respectively.
    The transistor 1 further comprises a P-type semiconductor element 33 in contact with the layer 15 in the domain 51 on the one hand, and in the domain 52 on the other hand. The semiconductor element 33 thus comprises a portion 331 in contact with the layer 15 in the domain 51, and a portion 332 in contact with the layer 15 in the domain 52. Moreover, the semiconductor element 33 is extends continuously between the portions 331 and 332, that is to say between the domains 51 and 52. The semiconductor element 33 is here formed so as to cover the insulating element 34. The semiconductor element 33 is projecting laterally beyond the insulating member 34, to form the portions 331 and 332 in contact with the layer 15. The semiconductor element 33 has a portion housed in the trench 5, which covers the side walls and the bottom wall of the insulating member 34.
    Part of the layer 15 is not covered by the layer 16, both in the domain 51 and in the domain 52. Each of these parts makes it possible: -to provide one of the edges of the element 34 covering a portion of layer 15; to provide contact between the portions 331 or 332 of the semiconductor element 33 and the layer 15; -to make contact with a gate insulator 32.
    The transistor 1 further comprises a gate insulator 32 formed on the semiconductor element 33 and protruding in contact with the layer 15 and against the end lateral faces of the semiconductor element 33. The transistor 1 further comprises a gate electrode 31 provided on the gate insulator 32. The gate electrode 31 is formed in line with the semiconductor element 33. In particular, the projection of the gate electrode 31 on the substrate 11 in a direction normal to this substrate 11 includes the projection of the semiconductor element 33 on the substrate 11 in the direction normal to this substrate 11. In addition, the gate electrode 31 has overflows 311 and 312 covering the grid insulator 32 which is in contact with the layer 15. These overflows 311 and 312 thus extend in depth between the layer 16 and the portions 331 and 332 respectively. These overflows 311 and 312 thus make it possible to apply an electromagnetic field laterally to the overflows 311 and 312.
    Thus, the semiconductor element 33 is well positioned in the electromagnetic field of the gate electrode 31 when it is polarized. The control electrode 31 may be made of the same material as for the first embodiment. The gate electrode 31 is electrically isolated from the drain 21 and the source 22 by an insulating layer 18, formed on the layers 15 and 16 in the continuity of the gate insulator 32. A control potential is applied selectively. on the gate electrode 31 via a control circuit not shown. In FIG. 7, transistor 1 is illustrated in its configuration in the open or blocked state. The insulating element 34 and the semiconductor element 33 make the transistor 1 of the normally open type, the conduction between the domains 51 and 52 being interrupted when a potential applied to the gate electrode 31 is lower than the threshold voltage .
    By applying a potential greater than the threshold voltage on the gate electrode 31, there is formed: an accumulation of electrons under the gate insulator 32 in contact with the layer 15. A conduction path is thus created between the electron gas layer 17 and the semiconductor element 33; an inversion channel in the semiconductor element 33. The semiconductor element 33 then becomes conductive. A conduction path is thus created between the portion 331 and the portion 332 through the semiconductor element 33. An electrical connection is thus created between the electron gas layer 17 of the domains 51 and 52. Conduction is thus provided between the drain 21 and the source 22 (as illustrated by the broken line).
    FIG. 8 is a logic diagram illustrating various steps of an exemplary method of manufacturing a transistor according to the invention.
    In a step 701, a superposition of a first layer of a III-V alloy semiconductor material and of a second layer of III-V alloy semiconductor material, forming a layer, is first provided. of electron gas at or near the interface between these first and second layers. This superposition of the first and second layers is for example formed in a manner known per se, for example by epitaxy. The first and second layers are for example formed on a stack of layers 11 to 14 as described with reference to the first to fourth embodiments. For a method of manufacturing an electron gas transistor, the first layer is of unintentionally doped type.
    In a step 702, a trench is formed separating the superposition of the first and second layers into disjoint first and second domains. The electron gas is interrupted by this trench, which passes through the first and second layers. The formation of the trench may be carried out in a manner known per se by photolithography and etching.
    In a step 703, a layer of electrical insulation is formed so as to cover the side walls and the bottom of the trench. The insulating layer can be deposited full plate, then shaped by photolithography and etching, so as to form an insulating member and to discover the upper surface of the second semiconductor layer, while retaining the insulator in the trenched to isolate the first and second domains.
    During a step 704, a semiconductor layer is formed so as to cover the insulating element. The semiconductor layer is then shaped by photolithography and etching, so as to form a semiconductor element having portions in contact with the first and second domains of the superposition. Moreover, the semiconductor element formed extends continuously over the insulating element between these portions in contact. This semiconductor layer is preferably deposited so as to exhibit doping as soon as it is deposited (P-type doping). The deposition of the semiconductor layer is for example carried out by a reactive cathode sputtering step.
    In a step 705, a gate insulator layer is formed to cover the semiconductor element.
    In a step 706, a gate electrode is formed on the gate insulator, directly above the semiconductor element. The formation of the gate electrode may include depositing a layer of polysilicon on the gate insulator layer, then a layer of a second insulator and a gate metal, and finally shaping of the deposited layer, by photolithography.
    In a step 707 the gate electrode is connected to a control circuit, configured to selectively apply a potential lower or higher than the threshold voltage.
    The steps of forming the drain and the source of the transistor are known per se to those skilled in the art, they are not detailed in the description of a method of manufacturing a transistor according to the invention.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Field-effect transistor (1) with high electron mobility of normally open type, characterized in that it comprises: a superposition of a first layer of semiconductor material (15) of the III-V alloy type and a second layer of semiconductor material (16) of alloy type III-V so as to form a layer of electron gas (17) at or near the interface between these first and second layers ; a trench (5) separating the superposition of the first and second layers of semiconductor material into first and second domains (51, 52); an insulating element (34) disposed in said trench so as to electrically isolate said first and second domains; a P-type doped semiconductor element (33) in contact with the first or second layer of semiconductor material (16) of the first and second domains (51, 52), and extending continuously between first and second domains on said insulating member (34); a gate insulator (32) disposed on the semiconductor element (33); a gate electrode (31) disposed on the gate insulator (32).
    [2" id="c-fr-0002]
    A field effect transistor (1) according to claim 1, wherein the P-type doped semiconductor element (33) is P-doped NiO.
    [3" id="c-fr-0003]
    The field effect transistors (1) according to claim 1, wherein the P-type doped semiconductor element (33) is of P-doped polysilicon.
    [4" id="c-fr-0004]
    4. The field effect transistors (1) according to claim 1, wherein the P-type doped semiconductor element (33) is of P-doped GaN.
    [5" id="c-fr-0005]
    A field effect transistor (1) according to any one of the preceding claims, wherein said P-type doped semiconductor element (33) extends into said trench (5).
    [6" id="c-fr-0006]
    A field effect transistor (1) according to any one of claims 1 to 4, wherein said insulating member (34) has a protrusion (341) protruding vertically from the trench (5), and wherein said semiconductor element -conducteur (33) covers said projection (341).
    [7" id="c-fr-0007]
    A field effect transistor (1) according to claim 6, further comprising a third layer of p-type doped semiconductor material (14) on which said first layer is formed, said trench (5) being extending into said third layer of semiconductor material, wherein said trench (5) has a depth of at least 100 nm and wherein said first layer of semiconductor material (15) has a thickness of at least 70 nm.
    [8" id="c-fr-0008]
    A field effect transistor (1) according to any one of the preceding claims, further comprising a third layer of p-type doped semiconductor material (14) on which said first layer is formed, said trench ( 5) extending into said third layer of semiconductor material.
    [9" id="c-fr-0009]
    A field effect transistor (1) according to claims 5 and 8, wherein the semiconductor element (33), the insulating element (34) and the gate insulator (32) are sufficiently thin for applying a threshold voltage on the gate electrode (31) creates an invert conduction channel in the third layer of semiconductor material (14) under said trench (5).
    [10" id="c-fr-0010]
    A field effect transistor (1) according to any one of the preceding claims, wherein the first layer of semiconductor material (15) is GaN.
    [11" id="c-fr-0011]
    A field effect transistor (1) according to any one of the preceding claims, wherein the second layer of semiconductor material (16) is AIGaN.
    [12" id="c-fr-0012]
    A field effect transistor (1) according to any one of the preceding claims, comprising a first conduction electrode (21) electrically connected to the electron gas of the first domain (51), and comprising a second conduction electrode ( 22) electrically connected to the electron gas of the second domain (52).
    [13" id="c-fr-0013]
    A field effect transistor (1) according to any one of the preceding claims, wherein said gate insulator (32) has a thickness of at most 15nm and / or wherein said semiconductor element (33) comprises a dopant concentration of type P at least equal to 2 * 1017cnr3.
    [14" id="c-fr-0014]
    A system, comprising: a field effect transistor (1) according to any one of the preceding claims; a control circuit configured to selectively apply a control voltage to said gate electrode (31), the magnitude of said control voltage generating a conductive inversion channel in said semiconductor element (33).
    [15" id="c-fr-0015]
    A method of manufacturing a heterojunction field effect transistor (1), comprising the steps of: providing a superposition of a first layer of semiconductor material (15, 65) of the III-V alloy type and a second layer of a III-V alloy-forming semiconductor material (16, 66) forming an electron gas layer (17) or a hole gas layer (67) at or near the interface of the interface between these first and second layers, a trench (5) separating the superposition of the first and second layers of semiconductor material into first and second domains (51, 52), an insulating element (34) being disposed in said trench (5) to electrically isolate said first and second domains from the superposition; forming a semiconductor element (33) in contact with the second layer of semiconductor material of the first and second domains (51, 52) and extending continuously between the first and second domains on the insulating element, semiconductor element (33) exhibiting P-type doping; forming a gate insulator (32) on the semiconductor element (33); forming a gate electrode (31) on the gate insulator (32) in line with the semiconductor element (33).
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    同族专利:
    公开号 | 公开日
    FR3050869B1|2018-05-18|
    EP3240041A1|2017-11-01|
    US10211305B2|2019-02-19|
    US20170330944A1|2017-11-16|
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    FR1653905A|FR3050869B1|2016-04-29|2016-04-29|NORMALLY OPEN TYPE HETEROJUNCTION TRANSISTOR WITH HIGH THRESHOLD VOLTAGE|
    FR1653905|2016-04-29|FR1653905A| FR3050869B1|2016-04-29|2016-04-29|NORMALLY OPEN TYPE HETEROJUNCTION TRANSISTOR WITH HIGH THRESHOLD VOLTAGE|
    EP17166076.4A| EP3240041A1|2016-04-29|2017-04-11|Normally-off heterojunction transistor with high threshold voltage|
    US15/581,620| US10211305B2|2016-04-29|2017-04-28|Normally-off hetrojunction transistor with high threshold voltage|
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